Damascene structure and method of making

ABSTRACT

A damascene structure with a plurality of low dielectric constant insulating layers acting as etch stops is disclosed. The selected low dielectric constant materials have similar methods of formation and similar capacities to withstand physical and thermal stress. In addition, the etchant used for each low dielectric constant insulating layer has a very small etching rate relative to the other low dielectric constant insulating layers. Thus, the low dielectric constant materials act as insulating layers through which trenches and vias are formed.

FIELD OF THE INVENTION

[0001] The present invention relates to semiconductor devices andmethods of making such devices. More particularly, the invention relatesto a method of forming damascene structures.

BACKGROUND OF THE INVENTION

[0002] The integration of a large number of components on a singleintegrated circuit (IC) chip requires complex interconnects. Ideally,the interconnect structures should be fabricated with minimal signaldelay and optimal packing density. The reliability and performance ofintegrated circuits may be affected by the qualities of theirinterconnect structures.

[0003] Advanced multiple metallization layers have been used toaccommodate higher packing densities as devices shrink below sub-0.25micron design rules. One such metallization scheme is a dual damascenestructure formed by a dual damascene process. The dual damascene processis a two-step sequential mask/etch process to form a two-levelstructure, such as a via connected to a metal line situated above thevia.

[0004] As illustrated in FIG. 1, a known dual damascene process beginswith the deposition of a first insulating layer 14 over a first levelinterconnect metal layer 12, which in turn is formed over or within asemiconductor substrate 10. A second insulating layer 16 is next formedover the first insulating layer 14. An etch stop layer 15 is typicallyformed between the first and second insulating layers 14, 16. The secondinsulating layer 16 is patterned by photolithography with a first mask(not shown) to form a trench 17 corresponding to a metal line of asecond level interconnect. The etch stop layer 15 prevents the upperlevel trench pattern 17 from being etched through to the firstinsulating layer 14.

[0005] As illustrated in FIG. 2, a second masking step followed by anetch step are applied to form a via 18 through the etch stop layer 15and the first insulating layer 14. After the etching is completed, boththe trench 17 and the via 18 are filled with metal 20, which istypically copper (Cu), to form a damascene structure 25, as illustratedin FIG. 3.

[0006] If desired, a second etch stop layer, such as stop layer 29 ofFIG. 4, may be formed between the substrate 10 and the first insulatinglayer 14 during the formation of a dual damascene structure 26. In anyevent, and in contrast to a single damascene process, the via and thetrench are simultaneously filled with metal. Thus, compared to thesingle damascene process, the dual damascene process offers theadvantage of process simplification and low manufacturing cost.

[0007] Dual damascene processes such as the ones described above posesignificant problems. One of the problems is caused by the use of one ormore etch stop layers. The etch stop layers 15, 25 prevent the damascenepatterns 17, 18 from extending into or through the underlying layers 14,10. Although the advantages of using the etch stop layers aresignificant, the process is complex since separate depositions arerequired for die etch stop layers.

[0008] In addition, the most commonly used etch stop material, siliconnitride (Si₃N₄), has a rather high dielectric constant (k)(approximately 7), which does not satisfy anymore the requirement ofresistance-capacitance delay regarding the parasitic capacitancegenerated by an intermetal insulating layer. As integrated circuitsbecome denser, it is increasingly important to minimize straycapacitance between the metal layers. This is accomplished by usingintermetal insulating layers that have a low dielectric constant, suchas, for example, organic dielectric materials. Silicon nitride does notsatisfy the requirement of small stray capacitance of advanced damascenestructures.

[0009] Accordingly, there is a need for an improved damascene processwhich reduces production costs and increases productivity. There is alsoa need for a damascene process that does not require etch stop layers,as well as a method for decreasing the stray capacitance between themetal layers of damascene structures.

SUMMARY OF THE INVENTION

[0010] The present invention provides a method for fabricating adamascene interconnect structure in a semiconductor device. According toone aspect of the invention, productivity can be increased since fewerprocessing steps are required. According to another aspect of theinvention, the use of high dielectric etch stop material may be avoided,so as to reduce or minimize stray capacitance.

[0011] In an exemplary embodiment, a plurality of low dielectricconstant materials are selected with similar methods of formation, aswell as with similar capacities to withstand physical and thermalstress. The low dielectric constant materials act as insulating layersthrough which trenches and vias are subsequently formed according todamascene processing. Since the low dielectric constant materials areselected so that the etchant available for each one has only a smalletch rate relative to the other low dielectric constant materials, theplurality of low dielectric constant materials act as etch stops duringthe fabrication of damascene structures. This way, the etch stop layersemployed in the prior art are eliminated and the number of fabricationsteps is reduced.

[0012] Additional advantages of the present invention will be moreapparent from the detailed description and accompanying drawings, whichillustrate preferred embodiments of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013]FIG. 1 is a cross sectional view of a semiconductor device at apreliminary stage of production.

[0014]FIG. 2 is a cross sectional view of the semiconductor device ofFIG. 1 at a subsequent stage of production.

[0015]FIG. 3 is a cross sectional view of the semiconductor device ofFIG. 2 at a subsequent stage of production.

[0016]FIG. 4 is a cross sectional view of another semiconductor device.

[0017]FIG. 5 is a cross sectional view of a semiconductor device at apreliminary stage of production and in accordance with a firstembodiment of the present invention.

[0018]FIG. 6 is a cross sectional view of the semiconductor device ofFIG. 5 at a subsequent stage of production.

[0019]FIG. 7 is a cross sectional view of the semiconductor device ofFIG. 6 at a subsequent stage of production.

[0020]FIG. 8 is a cross sectional view of the semiconductor device ofFIG. 7 at a subsequent stage of production.

[0021]FIG. 9 is a cross sectional view of the semiconductor device ofFIG. 8 at a subsequent stage of production.

[0022]FIG. 10 is a cross sectional view of the semiconductor device ofFIG. 9 at a subsequent stage of production.

[0023]FIG. 11 is a cross sectional view of the semiconductor device ofFIG. 10 at a subsequent stage of production.

[0024]FIG. 12 is a cross sectional view of the semiconductor device ofFIG. 11 at a subsequent stage of production.

[0025]FIG. 13 is a cross sectional view of the semiconductor device ofFIG. 12 at a subsequent stage of production.

[0026]FIG. 14 is a cross sectional view of the semiconductor device ofFIG. 13 at a subsequent stage of production.

[0027]FIG. 15 is a cross sectional view of the semiconductor device ofFIG. 14 at a subsequent stage of production.

[0028]FIG. 16 is a cross sectional view of a semiconductor deviceconstructed in accordance with a second embodiment of the presentinvention.

[0029]FIG. 17 illustrates a computer system having a memory cell with adual damascene structure according to the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0030] In the following detailed description, reference is made tovarious specific embodiments in which the invention may be practiced.These embodiments are described with sufficient detail to enable thoseskilled in the art to practice the invention, and it is to be understoodthat other embodiments may be employed, and that structural andelectrical changes may be made without departing from the spirit orscope of the present invention.

[0031] The term “substrate” used in the following description mayinclude any semiconductor-based structure that has a semiconductorsurface. The term should be understood to include silicon, silicon-oninsulator (SOI), silicon-on sapphire (SOS), doped and undopedsemiconductors, epitaxial layers of silicon supported by a basesemiconductor foundation, and other semiconductor structures. Thesemiconductor need not be silicon-based. The semiconductor could besilicon-germanium, germanium, or gallium arsenide. When reference ismade to a “substrate” in the following description, previous processsteps may have been utilized to form regions or junctions in or on thebase semiconductor or foundation.

[0032] The term “metal” is intended to include not only elemental metal,but also metal with other trace metals or in various alloyedcombinations with other metals as known in the art, as long as suchalloy retains the physical and chemical properties of the metal. Theterm “metal” is also intended to include oxides of such metals.

[0033] The present invention provides a method for fabricating adamascene interconnect structure in which a plurality of low dielectricconstant materials are selected with similar methods of formation, aswell as with similar capacities to withstand physical and thermalstress. The low dielectric constant materials act as insulating layersthrough which trenches and vias are subsequently formed.

[0034] Referring now to the drawings, where like elements are designatedby like reference numerals, FIG. 5 depicts a portion of a semiconductorsubstrate 50 on or within which a metal layer 52 has been formed. Themetal layer 52 represents a lower metal interconnect layer which is tobe later interconnected with an upper metal interconnect layer. Themetal layer 52 may be formed of copper (Cu), but other conductivematerials, such as tungsten (W) or aluminum (Al) and their alloys, maybe used also.

[0035] Referring now to FIG. 6, a first intermetal insulating layer 55is formed overlying the substrate 50 and the metal layer 52. In apreferred embodiment of the present invention, the first intermetalinsulating layer 55 is blanket deposited by spin coating to a thicknessof about 2,000 Angstroms to 15,000 Angstroms, more preferably about6,000 10,000 Angstroms. The first intermetal insulating layer 55 may becured at a predefined temperature, depending on the nature of thematerial. Other known deposition methods, such as sputtering by chemicalvapor deposition (CVD), plasma enhanced CVD (PECVD), or physical vapordeposition (PVD), may be used also for the formation of the firstintermetal insulating layer 55, as desired.

[0036] The first intermetal insulating layer 55 may be formed of a lowdielectric constant organic material such as, for example, polyimide,spin-on-polymers (SOP), flare, polyarylethers, parylene,polytetrafluoroethylene, benzocyclobutene (BCB) or SILK. Alternatively,the first intermetal insulating layer 55 may be formed of an inorganicmaterial with a low dielectric constant such as, for example,fluorinated silicon oxide (FSG), hydrogen silsesquioxane (HSQ) orNANOGLASS. The present invention is not limited, however, to theabove-listed materials and other organic and inorganic materials withlow dielectric constant may be used, especially ones whose dielectricconstant (k) is lower than that of silicon oxide (SiO₂), which isapproximately 4.0.

[0037] Next, as illustrated in FIG. 7, a second intermetal insulatinglayer 57 is formed overlying the first intermetal insulating layer 55and below a metal layer that will be formed subsequently. The secondintermetal insulating layer 57 may be formed, for example, by spincoating to a thickness of about 2,000 Angstroms to about 15,000Angstroms, more preferably of about 6,000-10,000 Angstroms. Followingdeposition, the second intermetal insulating layer 57 is cured at apredefined temperature, depending, again, on the nature and specificcharacteristics of the insulating material. Other deposition methods,such as the ones mentioned above with reference to the formation of thefirst intermetal insulating layer 55, may be used also.

[0038] The material of choice for the second intermetal insulating layer57 is also a low dielectric constant organic or inorganic material, witha dielectric constant lower than 4.0, as the ones listed above withreference to the first intermetal insulating layer 55. However, asdiscussed in more detail below, the two intermetal insulating layers 55,57 and the etch chemistries used to selectively remove these intermetalinsulating layers may be physically and functionally related to eachother. As such, the two insulating layers 55, 57 may be deposited in asimilar manner and by similar methods. In addition, the insulatinglayers 55, 57 are preferably compatible with each other in the sensethat each of them may be capable of withstanding stress levels whichwill be later induced as a result of various processes and during theuse of the IC device. Further, each material should be capable ofwithstanding the maximum temperature required in the processing of theother one.

[0039] In a preferred embodiment of the present invention, twocompatible materials for the two intermetal insulating layers 55, 57 areSILK (organic material with k of approximately 2.65 at 100 kHz) andNANOGLASS (inorganic material with k of approximately 3.5 at 100 kHz).Both SILK and NANOGLASS can be applied by spin coating and both arecapable of withstanding similar stress levels, as well as the processingtemperature of each other. Further, both SILK and NANOGLASS may beindividually etched by a respective etchant which, while readily etchingone insulating material, will have only a very small, negligible etchrate for the other insulating material.

[0040] Another example of two compatible low dielectric constantmaterials is a foamed polyimide (as the organic component with k in therange of 2.0 to 3.0, depending upon the degree of porosity) and hydrogensilsesquioxane (HSQ) (as the inorganic component with k in the range of2.3 to 3.0). However, other combinations may also be employed. Further,two low dielectric constant organic materials, as well as two lowdielectric constant inorganic materials may be used also, as long asboth materials retain compatible physical and chemical properties. Thus,the present invention is not limited to the use of the above-mentionedcombinations, and other compatible low dielectric constant materials maybe used also, especially those whose dielectric constants are lower than4.0.

[0041] As shown in FIG. 8, a first photoresist layer 58 is formed overthe second intermetal insulating layer 57 to a thickness of about 100 to120 Angstroms. The first photoresist layer 58 is then patterned with amask (not shown) having images of a via pattern 59. Thus, a via 65 a maybe formed, as shown in FIG. 9, by etching through the photoresist layer58 and into the second intermetal insulating layer 57. The etchant maybe selected in accordance with the characteristics of the secondinsulating material 57. The etchant (not shown) will selectively etchthe second insulating material 57 until it reaches the first insulatingmaterial 55. Then, the etch chemistry is changed, and a second etchantis employed to selectively etch the first intermetal insulating layer 55through to the metal layer 52. Thus, after the removal of the firstphotoresist layer 58, via 65 is formed into the first intermetalinsulating layer 55, as illustrated in FIG. 10.

[0042] In a preferred embodiment of the present invention, which employsthe SILK/NANOGLASS combination, the first etchant (for etching throughthe second intermetal insulating NANOGLASS layer 57) may contain achlorine (Cl) plasma. The second etchant (for selectively etching thefirst intermetal insulating SILK layer 55) may employ oxygen (O₂)plasma.

[0043] After the formation of the via 65 through the first intermetalinsulating layer 55, a trench 67 (FIG. 12) may be formed byphotolithography. As such, a second photoresist layer 62 (FIG. 11) isformed over the second intermetal insulating layer 57 to a thickness ofabout 100 to 120 Angstroms and then patterned with a mask (not shown)having images of a trench pattern 63. The trench pattern 63 is thenetched into the second intermetal insulating layer 57 to form trench 67,as shown in FIG. 12. The thickness of the first intermetal insulatinglayer 55 defines the thickness of the via 65 (FIGS. 10-12). Thethickness of the second intermetal insulating layer 57 defines thethickness of the trench 67 (FIG. 12).

[0044] The etching of the trench 67 is accomplished by employing, forexample, the first etchant (used for forming the via 65 a (FIG. 9)through the second insulating material 57) until the etching reaches thefirst insulating material 55. Thus, the etchant for forming the trench67 (FIG. 12) through the second intermetal insulating NANOGLASS layer 57may include chlorine plasma.

[0045] Subsequent to the formation of trench 67, the second photoresistlayer 62 is removed so that further steps to create the dual damascenestructure 100 (FIG. 15) may be carried out. As such, a barrier layer 72(FIG. 13) is formed on the via 65 and the trench 67, by CVD, PVD,sputtering or evaporation, to a thickness of about 50 Angstroms to about200 Angstroms, more preferably of about 100 Angstroms.

[0046] Preferred materials for the barrier layer 72 are metals, such astitanium (Ti), zirconium (Zr), tungsten (W), or hafnium (Hf), or metalcompounds, such as tantalum nitride (TaN) or silicon nitride (Si₃N₄). Ifdesired, the barrier layer 72 may be formed of refractory metalcompounds, such as refractory metal nitrides (for example TiN and HfN),refractory metal carbides (for example TiC or WC), or refractory metalborides (for example TiB or MoB). In any event, the barrier layer 72suppresses the diffusion of the metal atoms from the subsequentlydeposited conductive material (FIG. 14), while offering a lowresistivity and low contact resistance between the metal of the metallayer 52 and the barrier layer 72, and between the subsequentlydeposited conductive material (FIG. 14) and the barrier layer 72.

[0047] Although in a preferred embodiment of the invention the barrierlayer 72 is simultaneously deposited in both the via 65 and the trench67, the invention is not limited to this embodiment. Thus, the barrierlayer 72 may be deposited first in the via 65 before the formation ofthe trench 67, and then in the trench 67 after its respective formation.In this embodiment, the barrier layer 72 may be formed of a firstbarrier material corresponding to the via 65 and of a second barriermaterial corresponding to the trench 67. The first and second barriermaterials may be similar or different, depending on the characteristicsof the IC device.

[0048] As illustrated in FIG. 14, a conductive material 80 is nextdeposited to fill in both the via 65 and the trench 67. In the preferredembodiment, the conductive material 80 comprises either copper, tungstenor aluminum, but it must be understood that other materials may be usedalso. In any event, the conductive material 80 may be blanket depositedby a known PVD, CVD, or a combination of these techniques to fill inboth the via 65 and the trench 67. Alternatively, the conductivematerial 80 may be deposited by a plating technique.

[0049] After the deposition of the conductive material 80, excess metalformed above the surface of the second insulating material 57 may beremoved by either an etching or a polishing technique to form the dualdamascene structure 100 illustrated in FIG. 15. In a preferredembodiment of the present invention, chemical mechanical polishing (CMP)is used to polish away excess conductive material above the secondinsulating material 57 and the trench level. This way, the secondinsulating material 57 acts as a polishing stop layer when CMP is used.

[0050] Although only one dual damascene structure 100 is shown in FIG.15, it must be readily apparent to those skilled in the art that in factany number of such dual damascene structures may be formed on thesubstrate 50. Also, although the exemplary embodiment described aboverefers to the formation of a dual damascene structure 100, the inventionis further applicable to other types of damascene structures, forexample, single or triple damascene structures, depending on the numberof low dielectric constant insulating layers formed over the substrate50. For example, FIG. 16 illustrates a triple damascene structure 200with three low dielectric constant insulating layers 55, 57, 59 formedover the substrate 50 and in which vias and trenches are filledsimultaneously with the conductive material 80. Further, the inventionis not limited to the use of SILK and NANOGLASS, but may be used withother compatible organic and/or inorganic materials with dielectricconstants lower than 4.0.

[0051] In addition, further steps to create a functional memory cell maybe carried out. Thus, additional multilevel interconnect layers andassociated dielectric layers could be formed to create operativeelectrical paths from the dual damascene structure 100 to a source/drainregion (not shown) of the substrate 50.

[0052] A typical processor-based system 400 which includes a memorycircuit 448, for example a DRAM, containing dual damascene structuresaccording to the present invention is illustrated in FIG. 17. Aprocessor system, such as a computer system, generally comprises acentral processing unit (CPU) 444, such as a microprocessor, a digitalsignal processor, or other programmable digital logic devices, whichcommunicates with an input/output (I/O) device 446 over a bus 452. Thememory 448 communicates with the system over bus 452.

[0053] In the case of a computer system, the processor system mayinclude peripheral devices such as a floppy disk drive 454 and a compactdisk (CD) ROM drive 456 which also communicate with CPU 444 over the bus452. Memory 448 is preferably constructed as an integrated circuit,which includes one or more dual damascene structures 100. If desired,the memory 448 may be combined with the processor, e.g. CPU 444, in asingle integrated circuit.

[0054] The above description and drawings are only to be consideredillustrative of exemplary embodiments which achieve the features andadvantages of the present invention. Modification and substitutions tospecific process conditions and structures can be made without departingfrom the spirit and scope of the present invention. Accordingly, theinvention is not to be considered as being limited by the foregoingdescription and drawings, but is only limited by the scope of theappended claims.

What is claimed as new and desired to be protected by Letters Patent ofthe United States is:
 1. A method of forming a damascene structure, saidmethod comprising the steps of: forming a first opening through a firstinsulating layer; forming a second opening through a second insulatinglayer which is provided over said first insulating layer, said firstopening being in communication with said second opening, wherein atleast one of said first and second insulating layers includes a lowdielectric constant material; and providing a conductive material insaid first and second openings.
 2. The method of claim 1, wherein saidfirst insulating layer includes organic material.
 3. The method of claim2, wherein said organic material is selected from the group consistingof polyimide, spin-on-polymers, flare, polyarylethers, parylene,polytetrafluoroethylene, benzocyclobutene and SILK.
 4. The method ofclaim 2 further comprising the step of forming said first insulatinglayer of SILK.
 5. The method of claim 1 further comprising the step offorming said first insulating layer of a low dielectric constantinorganic material.
 6. The method of claim 5, wherein said inorganicmaterial is selected from the group consisting of fluorinated siliconoxide, hydrogen silsesquioxane and NANOGLASS.
 7. The method of claim 5,wherein said first insulating layer is formed of NANOGLASS.
 8. Themethod of claim 1, wherein said first insulating layer is formed bydeposition to a thickness of about 2,000 to 15,000 Angstroms.
 9. Themethod of claim 8, wherein said first insulating layer is formed bydeposition to a thickness of about 6,000 to 10,000 Angstroms.
 10. Themethod of claim 1 further comprising the step of forming said secondinsulating layer of a low dielectric constant organic material.
 11. Themethod of claim 10, wherein said low dielectric constant organicmaterial is formed of a material selected from the group consisting ofpolyimide, spin-on-polymers, flare, polyarylethers, parylene,polytetrafluoroethylene, benzocyclobutene and SILK.
 12. The method ofclaim 10 further comprising the step of forming said second insulatinglayer of SILK.
 13. The method of claim 1 further comprising the step offorming said second insulating layer of a low dielectric constantinorganic material.
 14. The method of claim 13, wherein said inorganicmaterial is formed of a material selected from the group consisting offluorinated silicon oxide, hydrogen silsesquioxane and NANOGLASS. 15.The method of claim 13, wherein said second insulating layer is formedof NANOGLASS.
 16. The method of claim 1, wherein said second insulatinglayer is formed by deposition to a thickness of about 2,000 to 15,000Angstroms.
 17. The method of claim 16, wherein said second insulatinglayer is formed by deposition to a thickness of about 6,000 to 10,000Angstroms.
 18. The method of claim 1, wherein said first and secondinsulating layers are formed of different materials which can beselectively etched relative to each other.
 19. The method of claim 18,wherein said step of forming said first opening is achieved byselectively etching said second insulating layer with a first etchchemistry and then selectively etching said first insulating layer witha second etch chemistry.
 20. The method of claim 19, wherein said stepof forming said second opening is achieved by selectively etching saidsecond insulating layer with said first etch chemistry.
 21. The methodof claim 1, wherein said conductive material is blanket deposited. 22.The method of claim 1, wherein said conductive material is formed of amaterial selected from the group consisting of copper, copper alloy,gold, gold alloy, silver, silver alloy, tungsten, tungsten alloy,aluminum, and aluminum alloy.
 23. The method of claim 1 furthercomprising the step of chemical mechanical polishing said conductivematerial.
 24. The method of claim 1 further comprising the step offorming a barrier layer before said step of locating said conductivematerial.
 25. A method of forming a dual damascene structure, saidmethod comprising the steps of: forming a SILK insulating layer over atleast a portion of a metal layer provided within a substrate; forming aNANOGLASS insulating layer in contact with said SILK insulating layer;forming a first opening within said SILK insulating layer and extendingsaid opening to said metal layer; forming a second opening within saidNANOGLASS insulating layer and extending said second opening to saidfirst opening; and depositing a conductive material in said first andsecond openings.
 26. The method of claim 25, wherein said SILKinsulating layer is formed by deposition to a thickness of about 2,000to 15,000 Angstroms.
 27. The method of claim 26, wherein said SILKinsulating layer is formed by deposition to a thickness of about 6,000to 10,000 Angstroms.
 28. The method of claim 25, wherein said NANOGLASSinsulating layer is formed by deposition to a thickness of about 2,000to 15,000 Angstroms.
 29. The method of claim 28, wherein said NANOGLASSinsulating layer is formed by deposition to a thickness of about 6,000to 10,000 Angstroms.
 30. The method of claim 25, wherein said step offorming said first opening is achieved by selectively etching saidNANOGLASS insulating layer relative to said SILK layer with a first etchchemistry, and then selectively etching said SILK insulating layerrelative to said metal layer with a second etch chemistry.
 31. Themethod of claim 30, wherein said step of forming said second opening isachieved by selectively etching said NANOGLASS insulating layer relativeto said SILK layer with said first etch chemistry.
 32. The method ofclaim 31, wherein said first etch chemistry is a chlorine plasmachemistry and said second etch chemistry is an oxygen plasma chemistry.33. The method of claim 25, wherein said conductive material is blanketdeposited.
 34. The method of claim 25, wherein said conductive materialis formed of a material selected from the group consisting of copper,copper alloy, gold, gold alloy, silver, silver alloy, tungsten, tungstenalloy, aluminum, and aluminum alloy.
 35. The method of claim 25 furthercomprising the step of chemical mechanical polishing said conductivematerial.
 36. The method of claim 25 further comprising the step offorming a barrier layer before said step of depositing said conductivematerial.
 37. An integrated circuit structure, comprising: a firstinsulating layer with a dielectric constant lower than 4.0 provided overa semiconductor substrate and contacting at least a portion of a metallayer provided within said semiconductor substrate; and a secondinsulating layer with a dielectric constant lower than 4.0 provided oversaid first insulating layer, said second and first insulating layersbeing capable of withstanding similar stress levels and processingtemperatures.
 38. The integrated circuit structure of claim 37, whereinsaid first insulating layer includes organic material.
 39. Theintegrated circuit structure of claim 38, wherein said organic materialis selected from the group consisting of polyimide, spin-on-polymers,flare, polyarylethers, parylene, polytetrafluoroethylene,benzocyclobutene and SILK.
 40. The integrated circuit structure of claim38, wherein said first insulating layer includes SILK material.
 41. Theintegrated circuit structure of claim 37, wherein said first insulatinglayer includes inorganic material.
 42. The integrated circuit structureof claim 41, wherein said inorganic material is selected from the groupconsisting of fluorinated silicon oxide, hydrogen silsesquioxane andNANOGLASS.
 43. The integrated circuit structure of claim 37, whereinsaid first insulating layer has a thickness of about 2,000 to 15,000Angstroms.
 44. The integrated circuit structure of claim 37, whereinsaid second insulating layer is a low dielectric constant organicmaterial layer.
 45. The integrated circuit structure of claim 44,wherein said low dielectric constant organic material layer is formed ofa material selected from the group consisting of polyimide,spin-on-polymers, flare, polyarylethers, parylene,polytetrafluoroethylene, benzocyclobutene and SILK.
 46. The integratedcircuit structure of claim 37, wherein said second insulating layer is alow dielectric constant inorganic material layer.
 47. The integratedcircuit structure of claim 46, wherein said inorganic material layer isformed of a material selected from the group consisting of fluorinatedsilicon oxide, hydrogen silsesquioxane and NANOGLASS.
 48. The integratedcircuit structure of claim 37, wherein said second insulating layer hasa thickness of about 2,000 to 15,000 Angstroms.
 49. The integratedcircuit structure of claim 37, wherein said first and second insulatinglayers are formed of different materials which can be selectively etchedrelative to each other.
 50. A dual damascene structure, comprising: asubstrate; a metal layer provided within said substrate; a first lowdielectric constant insulating layer located over said substrate; a viafilled with a conductive material, said via being situated within saidfirst low dielectric constant insulating layer and extending to at leasta portion of said metal layer; a second low dielectric constantinsulating layer located over said first low dielectric constantinsulating layer; a trench filled with said conductive material, saidtrench being situated within said second low dielectric constantinsulating layer and extending to said via.
 51. The dual damascenestructure of claim 50, wherein said first low dielectric constantinsulating layer is a low dielectric constant organic material layer.52. The dual damascene structure of claim 51, wherein said lowdielectric constant organic material layer is formed of a materialselected from the group consisting of polyimide, spin-on-polymers,flare, polyarylethers, parylene, polytetrafluoroethylene,benzocyclobutene and SILK.
 53. The dual damascene structure of claim 50,wherein said first low dielectric constant insulating layer is a lowdielectric constant inorganic material layer.
 54. The dual damascenestructure of claim 53, wherein said inorganic material layer is formedof a material selected from the group consisting of fluorinated siliconoxide, hydrogen silsesquioxane and NANOGLASS.
 55. The dual damascenestructure of claim 50, wherein said first low dielectric constantinsulating layer has a thickness of about 2,000 to 15,000 Angstroms. 56.The dual damascene structure of claim 50, wherein said second lowdielectric constant insulating layer is a low dielectric constantorganic material layer.
 57. The dual damascene structure of claim 56,wherein said low dielectric constant organic material layer is formed ofa material selected from the group consisting of polyimide,spin-on-polymers, flare, polyarylethers, parylene,polytetrafluoroetliylene, benzocyclobutene and SILK.
 58. The dualdamascene structure of claim 50, wherein said second low dielectricconstant insulating layer is a low dielectric constant inorganicmaterial layer.
 59. The dual damascene structure of claim 58, whereinsaid inorganic material layer is formed of a material selected from thegroup consisting of fluorinated silicon oxide, hydrogen silsesquioxaneand NANOGLASS.
 60. The dual damascene structure of claim 50, whereinsaid second low dielectric constant insulating layer has a thickness ofabout 2,000 to 15,000 Angstroms.
 61. The dual damascene structure ofclaim 50, wherein said metal layer is formed of a material selected fromthe group consisting of metals, metal oxides and metal alloys.
 62. Thedual damascene structure of claim 50, wherein said conductive materialis formed of a material selected from the group consisting of copper,copper alloy, gold, gold alloy, silver, silver alloy, tungsten, tungstenalloy, aluminum, and aluminum alloy.
 63. The dual damascene structure ofclaim 50, wherein said first low dielectric constant insulating layer isa SILK layer and said second low dielectric constant insulating layer isa NANOGLASS layer.
 64. The dual damascene structure of claim 50, whereinsaid first low dielectric constant insulating layer is a foamedpolyimide layer and said second low dielectric constant insulating layeris a hydrogen silsesquioxane layer.
 65. The dual damascene structure ofclaim 50, wherein said substrate is a semiconductor substrate.
 66. Thedual damascene structure of claim 50, wherein said first and second lowdielectric constant insulating layers are formed of different materialswhich can be selectively etched relative to each others.
 67. Aprocessor-based system, comprising: a processor; and an integratedcircuit coupled to said processor, at least one of said processor andintegrated circuit including a damascene structure, said damascenestructure comprising a first low dielectric constant insulating layerwith a via formed within said first low dielectric constant insulatinglayer and extending to at least a portion of a metal layer providedwithin a semiconductor substrate, and a second low dielectric constantinsulating layer over said first low dielectric constant insulatinglayer with a trench formed within said second low dielectric constantinsulating layer and extending to said via.
 68. A damascene structure ona semiconductor substrate, comprising: at least a first insulating layerwith a dielectric constant lower than that of silicon oxide providedover said semiconductor substrate and contacting at least a portion of ametal layer; at least a second insulating layer located over said firstinsulating layer; and at least a third insulating layer located oversaid second insulating layer, said first, second, and third insulatinglayers being capable of withstanding similar stress levels andprocessing temperatures.
 69. The damascene structure of claim 68 furthercomprising at least one via formed in at least one of said first, secondand third insulating layers.
 70. The damascene structure of claim 69,wherein said via is filled with a conductive material.